FIG. 5 shows a prior art semiconductor device including a PHS. In FIG. 5, reference numeral 1 designates a semiconductor device obtained by mounting a semiconductor chip 5 on a carrier 7, such as Cu or, by solder 6. The semiconductor chip 5 includes a semiconductor chip substrate 3, such as Si or GaAs, function element layers 2 and a PHS 4 at the rear of semiconductor chip substrate 3 formed by Au, Ag, or Cu plating.
The prior art production method for the semiconductor device is be described with reference to FIGS. 6(a) to 6(d).
An initial semiconductor substrate 8, such as Si or GaAs, having a thickness of about 600 microns has active elements and passive elements produced at its surface and thereafter, a function element layer 2 is prepared by on the substrate 8 (FIG. 6(a)).
Next, the semiconductor wafer substrate 8 is thinned to a predetermined thickness with due regard to heat radiation and mounting work, that is, to about 100 microns by lapping, polishing, or etching. Thereafter, a Ti, Ni, or Cr layer that adheres well to the substrate 8 is deposited in an evaporative process on the rear surface of substrate 8. A rear surface electrode 9 comprising an Au layer with a thickness of about 3000 angstroms is deposited by electroless plating (FIG. 6(b)).
Thereafter, a PHS 4 comprising a Au layer with a thickness of about 40 to 50 microns is deposited on the rear surface electrode 9 by an electrolytic plating (FIG. 6(c)). Finally, the semiconductor wafer substrate 8 and the PHS 4 are cut along a predetermined cutting line by, for example, a dicer, whereby semiconductor chips 5 are produced (FIG. 6(d)).
Another prior art production method for the semiconductor device is be described with reference to FIGS. 7(a) to 7(d).
The production processes before the deposition of the rear surface electrode 9 at the rear surface of the semiconductor wafer 8 (FIGS. 7(a) and 7(b)) are the same as those shown in FIGS. 6(a) and 6(b).
After the rear surface electrode 9 is produced, a PHS photoresist pattern 10 is deposited on the rear surface of substrate 8 corresponding to the chip patterns of the function element layer 2, that is, element patterns of active elements, passive elements, or a wiring layer (FIG. 7(b)). Thereafter, PHS 4 is selectively produced, using the photoresist pattern 10 as a mask, by electrolytic plating and the photoresist pattern 10 is removed (FIG. 7(c)). Finally, the rear surface electrode 9 and the semiconductor wafer substrate 8 are successively etched, whereby a semiconductor chips 5 are produced.
In this method, the outer configuration size of PHS 4 is more or less larger than the semiconductor chip substrate 3 as shown in FIG. 7(d). As shown in FIG. 9, the distance l from the edge of semiconductor chip substrate 3 to the edge of PHS 4 is determined in accordance with he thickness D of PHS 4. For example, when the thickness D is 40 to 50 microns and the photoresist pattern thickness d is 3 to 10 microns, the distance l is at most 30 to 35 microns.
The semiconductor chip 5 produced by the method shown in FIG. 6 or 7 is mounted on the carrier 7 using soldering material 6 as shown in FIG. 5.
Firstly, the carrier 7 is heated, and soldering material 6 is applied on the entire surface of carrier 7. Thereafter, the semiconductor chip 5 is picked up using tweezers 30, as shown in FIGS. 11(a) and 11(b), and put on the carrier 7. The chip 5 is scrubbed on the carrier 7 such that the oxide film at the surface of soldering material 6 is forced aside thereby bringing the rear surface of chip 5 into contact with the active soldering material 6 below the oxide film. Thereafter, the device is cooled, and the semiconductor device 1 is completed.
In the prior art semiconductor chip of such construction, there are problems in handling and semiconductor chip during adhering of the semiconductor chip to a carrier using solder.
(1) In the semiconductor chip 5 produced by the method shown in FIGS. 6(a)-(d), the area of the PHS 4 and of the semiconductor chip substrate 3, that is, the outer configuration sizes thereof are equal to each other and the side surfaces thereof are approximately flush. Therefore, while placing the semiconductor chip 5 on the carrier 7, cracking or chipping of the semiconductor chip substrate 3 can occur from tweezers 30 or a collet (not shown) that contacts the semiconductor chip substrate 3 as shown in FIG. 11(a), damaging the device.
In the semiconductor chip 5 produced by the method shown in FIG. 7, although the outer configuration size of the PHS 4 is more or less larger than that of the semiconductor chip substrate 3, since the PHS 4 consists of a soft material such as gold, the PHS 4 is deformed when it is picked up by tweezers 30, and the tweezers 30 come in contact with the semiconductor chip substrate 3 as shown in FIG. 11(b), damaging substrate 3.
(2) When the semiconductor chip 5 is soldered onto the carrier 7, the temperature is raised to about 300.degree. to 400.degree. C. and the semiconductor chip substrate 3 is deformed due to the difference in the thermal expansion coefficients of the semiconductor chip substrate 3, the PHS 4, and the carrier 7. To be more precise, the thermal expansion coefficient of the semiconductor chip substrate (GaAs) 3 (5.5.times.10.sup.-6 /.degree. C.) is lower than that of PHS (Au) 4 (15.4.times.10.sup.-6 /.degree. C.) and that of the carrier (Cu) 7 (18.3.times.10.sup.-6 /.degree. C.). As shown in FIG. 10(a), the chip 5 is deformed upon receiving the force F so that both sides warp at high temperature. Such a deformed chip 5 is mounted onto the carrier with a residual stress applied to the semiconductor substrate 3, causing deterioration of the operating characteristics and reliability of the device.